This application claims priority from Korean Patent Application No. 2001-55012, filed on Sep. 7, 2001, the contents of which are herein incorporated by reference in their entirety.
Embodiments of the present invention relate to a non-volatile semiconductor memory device, and, more specifically, relate to a NAND type of a flash EEPROM device with good program inhibition characteristics. In addition, embodiments of the invention are directed to a method of programming a NAND type flash EEPROM device.
FIG. 1 is a block diagram of a conventional NAND type flash EEPROM device. Referring to FIG. 1, the flash memory device includes a memory cell array 10, a high voltage pump circuit 20, a row pre-decoder 30, a row decoder 40, and a page buffer and column decoder block 50.
The memory cell array 10 is formed of a plurality of memory cell blocks. Each of the memory cell blocks includes a plurality of memory cell strings (so-called xe2x80x9cNAND stringsxe2x80x9d). Each cell string includes several floating gate transistors TC1 to TC16 or TC17 to TC32, as memory cells. Channels of the respective floating gate transistors TC1 to TC16 or TC17 to TC32 are connected in series between a channel of a string select transistor TS1 or TS2 and a channel of a ground select transistor TG1 or TG2.
Each block of the memory cell array 10 further includes a string select line SSL, a ground select line GSL, word lines WL1 to WL16, and bit lines BL1 to BLn. The string select line SSL is connected in common with gates of string select transistors TS1, . . . , TS2. Each word line WL1, WL2, . . . , or WL16 is connected in common to control electrodes of corresponding floating gate transistors (e.g., TC1, . . . , TC17). A word line and a plurality of corresponding floating gate transistors connected thereto are normally called a xe2x80x9cpagexe2x80x9d. Conventionally, an appropriate number of pages (e.g., 8 or 16 pages) constitute a single cell block in the memory cell array 10. The ground select line GSL is connected in common to gates of a plurality of ground select transistors TG1, . . . , TG2. Each of the bit lines BL1, . . . and BLn is connected to a corresponding cell string.
The high voltage pump circuit 20 generates a high voltage VPP needed in a write operation (generally, erasing plus programming) of memory cells. The row pre-decoder 30 receives the high voltage VPP from the high voltage pump circuit 20, and drives a global string select line and a global ground select line in response to a string select line enable signal and a ground select line enable signal, respectively. In addition, the row pre-decoder 30 drives global word lines corresponding to a single memory cell block selected by address signals. Voltages on the global string select line, the global word lines and the global ground select line are transferred onto corresponding lines of the selected memory cell block (i.e., the string select line SSL, word lines WL1 to WL16, and the ground select line GSL), in control of the row decoder 40, respectively. The page buffer and column decoder block 50 either senses and provides voltages on the bit lines to outside the memory device, or transfers voltages from outside the memory device onto the bit lines.
The above-described conventional flash memory device may employ a program inhibition technique using either a self-boosting or a local self-boosting in order to inhibit unwanted memory cells from being programmed during a program operation. Examples of program inhibition technique using a self-boosting are found in U.S. Pat. No. 5,677,873 and U.S. Pat. No. 5,991,202. The program inhibition technique using a local self-boosting is disclosed in, for example, U.S. Pat. No. 5,715,194 and U.S. Pat. No. 6,061,270.
Notwithstanding adoption of such program inhibition techniques, a capacitive coupling between adjacent signal lines increases with a decrease in a space interval between adjacent signal lines, due to a present trend toward a high integration. This coupling may cause a program inhibition failure or a program failure.
FIG. 2 is a timing diagram of a program operation of the flash memory device of FIG. 1. Referring now to FIGS. 1 and 2, a program operation of the flash memory device will be described in detail.
As is known to those skilled in the art, first, cell transistors TC1 to TC32 are commonly erased to have negative threshold voltages prior to a beginning of a program operation of the NAND type flash memory device.
During a program operation, the power supply voltage VCC and the ground voltage VSS (or 0V) are applied to a string select line SSL and a ground select line GSL, respectively. In addition, the power supply voltage VCC and the ground voltage VSS are respectively applied to a bit line BL1 corresponding to a program inhibited string (TS1, TC1 to TC16, TG1) and a bit line BLn corresponding to a programmed string (TS2, TC17 to TC32, TG2). Accordingly, channel voltages of respective cell transistors TC1 to TC16 are increased up to VCCxe2x88x92Vth, where Vth is a threshold voltage of the string select transistor TS1.
Once the channel voltages of the respective cell transistors TC1 to TC16 go up to VCCxe2x88x92Vth, string select transistor TS1 is substantially shut off since a source-gate voltage of the transistor TS1 does not exceed its threshold voltage Vth. This results in an electrical insulation between the cell transistors TC1 to TC16 and the bit line BL1. In addition, with the application of the ground voltage VSS to the ground select line GSL, the ground select transistor TG1 is in a turn-off state, and thus channels of the cell transistors TC1 to TC16 are in a floating state.
In such a state, when a pass voltage Vpass is applied to the word lines WL2 to WL16 connected to the memory cell transistors TC2 to TC16 and TC18 to TC32 that are not intended to be programmed, a capacitive coupling between the word lines WL2 to WL16 and the cell transistors TC1 to TC16 may cause channel voltages of the respective cell transistors TC1 to TC16 held in a floating state to be boosted. This reduces a voltage difference between floating gates and channels of the program inhibited cell transistors TC1 to TC16, thereby preventing the occurrence of an F-N tunneling therebetween. As a result, the program inhibited cell transistors TC1 to TC16 may be maintained in an erased state.
Thereafter, to program the memory cell transistor TC17, a program voltage Vpgm may be applied to the word line WL1 connected to the cell transistor TC17. In such a case, a rise time of the program voltage Vpgm may be about 1 to 2 microseconds.
As mentioned before, however, a capacitive coupling between adjacent signal lines increases with a decrease in the space interval between the signal lines, due to parasitic capacitors 12, C1 to C16 located between the signal lines as shown in FIG. 1.
Accordingly, in such a highly integrated memory device of FIG. 1, when a program voltage Vpgm is supplied to a word line (e.g., WL1) adjacent to the string select line SSL in order to program a cell transistor (e.g., TC17) coupled to the word line, a voltage on the string select line SSL may increase by a coupling voltage Vcpl from the power supply voltage VCC, as shown in FIG. 2, because of a capacitive coupling between the word line and the string select line or because of a parasitic capacitor C1, which results from an abrupt rise of the program voltage Vpgm, so that the string select transistor TS1 will turn on. As a result, electric charges induced on channels of the program inhibited cell transistors (e.g., TC1 to TC16) will move to a corresponding bit line (e.g., BL1), so channel voltages of the program inhibited cell transistors will become lower and the voltage difference between the word lines WL1 to WL16 and the channels of the cell transistors TC1 to TC16 will increase. This will consequently result in a program inhibition failure or program disturb of the cell transistors TC1 to TC16.
Based upon the above and foregoing, it can be appreciated that there presently exists a need in the art for a NAND type of a nonvolatile flash memory device which eliminates the above-described drawbacks and shortcomings of the presently available NAND type flash memory devices.
Embodiments of the invention provide a NAND type of a non-volatile flash memory device with improved program inhibition characteristics and a method of efficiently programming the same.
According to an aspect of the present invention, a non-volatile integrated circuit memory device includes a first select line, a first select transistor, a word line adjacent to and disposed in parallel with the first select line, a non-volatile memory cell transistor, a second select line, a second select transistor, and a high voltage pump circuit.